A field-programmable gate array (FPGA) is an integrated circuit designed to be reconfigured by the user after manufacturing to build a System-on-Chip (SoC) embedded device. The needed logic is usually implemented as a software image and then instantiated on the FPGA to inherit the nice properties of hardware, like higher speed and better security. Unfortunately, since the image itself, e.g., a Softcore that represents a Processing Unit, is a software, it is prone to faults and vulnerabilities that manifest after instantiation on the FPGA. Unfortunately, an Advanced Persistent Threat (APT) is possible if a determined adversary managed to discover a new vulnerability to initiate a zero-day, leaving no chance for classical detection and prevention tools to recover. In addition, the softcore can include bugs and glitches that manifest only at run time. Fault and Intrusion Tolerance (FIT) is a technique used to make a process resilient to such attacks by masking them. A FIT protocol replicates the processors, i.e., a softcore in our case, by running three versions simultaneously, and collecting a majority agreement (or consensus) on each operation. If the majority (e.g., 2/3 processors) did not fail at the same instant, the fault is masked, and the SoC continues operation as designed. This requires some level of diversity in the running softcore to increase the chances of independence of failures.