Rejuvenation of Diverse FPGA Softcores in a SoCApply
A field-programmable gate array (FPGA) is an integrated circuit designed to be reconfigured by the user after manufacturing to build a System-on-Chip (SoC) embedded device. The needed logic is usually implemented as a software image and then instantiated on the FPGA to inherit the nice properties of hardware, like higher speed and better security. Unfortunately, since the image itself, e.g., a Softcore that represents a Processing Unit, is a software, it is prone to faults and vulnerabilities that manifest after instantiation on the FPGA. Unfortunately, an Advanced Persistent Threat (APT) is possible if a determined adversary managed to discover a new vulnerability to initiate a zero-day, leaving no chance for classical detection and prevention tools to recover. In addition, the softcore can include bugs and glitches that manifest only at run time. Fault and Intrusion Tolerance (FIT) is a technique used to make a process resilient to such attacks by masking them. A FIT protocol replicates the processors, i.e., a softcore in our case, by running three versions simultaneously, and collecting a majority agreement (or consensus) on each operation. If the majority (e.g., 2/3 processors) did not fail at the same instant, the fault is masked, and the SoC continues operation as designed. This requires some level of diversity in the running softcore to increase the chances of independence of failures.
Program - Computer Science
Division - Computer, Electrical and Mathematical Sciences and Engineering
Faculty Lab Link - https://cemse.kaust.edu.sa/rc3
Center Affiliation - Resilient Computing and Cybersecurity Center
Field of Study - FPGA, System on Chip, Replication
Professor, Computer Science and Director, Resilient Computing and Cybersecurity Center (Computer, Electrical and Mathematical Science and Engineering Division)
Desired Project Deliverables
The goal of this project is to experiment running an FIT we are implementing on a diverse softcores, e.g., Microblaze, RISC-V, Openpiton, etc., on an FPGA and simulate some fault or attacks. We are experimenting the concept on a Xilinx Zinc board using equivalent replicas. The objectives are to check the feasibility of running the FIT with different softcore types and evaluate the behavior in action. The intern will acquire all this knowledge and publish the results by working with a team of experts.